ST2022-6 Decapsulator Core implements SMPTE ST2022-6 specification along with ST2022-7 for redundancy.

ST2022-6 specifies transport of SDI raster data over IP transport protocols. It specifies how SDI raster data is packetized and encapsulated for transmission as IP Packets. Our core is scalable, configurable and can be customized to suit any customer requirement for supporting various platforms, features and integration to a large design. We have system level self-checking testbenches to verify all the functionalities and is included with the design apart from hardware validation done in FPGA platform. The core can be scaled to accommodate any number of decapsulators with resources being the only limiting factor. The interfaces to the cores currently support AXI interfaces for packet data interfaces, but may be adapted to other interfaces as customer needs change. This core is part of the larger IP core which is able to support both ST2110 and ST2022-6 in a single core without much, if any, increase in core gate count.

ST 2022-6 Decapsulator Features :-

• Implements SMPTE standard ST2022-6 (High Bit Rate Media Signals over IP Networks)
• Scalable to any number of Decapsulators at compile time
• Supports redundancy (SMPTE ST 2022-7)
• Tested for ASIC and FPGA platforms
• Integration support available
• Memory usage is configurable
• Implemented in System Verilog
• SMPTE 2110 streams may be supported along with 2022-6
• Supports 25 GHz interface bandwidth on the IP interface side
• Comes with self-checking Testbenches for verification