ST2110 Decapsulator Core implements SMPTE ST2110 specifications. This core is part of cores which support both ST2110 and ST2022-6 implementations in a single core.

ST2110 is a collection of standards detailing different aspects of utilizing IP transport protocols for video/audio/ancillary transports. It specifies how video and audio are synchronized between sources and receivers and how the video, audio, ancillary data are encapsulated for transmission as IP packets. Our core is scalable, configurable and can be customized to suit any customer requirement for supporting various platforms, features and integration to a large design. We have system level self-checking testbenches to verify all the functionalities and is included with the design apart from hardware validation done in FPGA platform. The core can be scaled to accommodate any number of decapsulators with resources being the only limiting factor. The interfaces to the cores currently support AXI interfaces for packet data interfaces, but may be adapted to other interfaces as customer needs change. This core is part of the larger IP core which is able to support both ST2110 and ST2022-6 in a single core without much, if any, increase in core gate count.

ST 2110 Decapsulator Features :-

• Implements SMPTE standard ST2110 (collection of standards)
• Audio, Video, Ancillary data is supported
• Scalable to any number of Decapsulators at compile time
• Supports redundancy (SMPTE ST 2022-7)
• Tested for ASIC and FPGA platforms
• Integration support available
• Memory usage is configurable
• Implemented in System Verilog
• SMPTE 2022-6 streams may be supported along with 2110
• Supports 25 GHz interface bandwidth on the IP interface side
• Comes with self-checking Testbanches for verification